The present invention relates to a semiconductor integrated circuit, and more particularly to technology effectively applicable to a semiconductor integrated circuit with a zigzag arrangement of bonding pads.
A typical gate array logic LSI has a logic portion formed of a matrix of many basic cells arranged in the central portion of the main surface of a semiconductor chip. A plurality of input/output buffer circuits are arranged outside the logic portion in such a way as to surround the logic portion. Further, a plurality of bonding pads (external terminals) for providing electrical connection with an external unit are arranged outside the input/output buffer circuits, that is, on the outermost peripheral portion of the semiconductor chip. These bonding pads are arranged in positions corresponding to the positions of the input/output buffer circuits. A logic LSI using a gate array system has been described in U.S. Pat. No. 5,075,753, for example.
In a current logic LSI of the sort that uses such a gate array system, two or three lines of bonding pads are arranged along the outer periphery of a semiconductor chip to deal with an increase in the number of external terminals resulting from a demand for a gate which is larger in scale. Further, the bonding pads are arranged in a zigzag manner by shifting the line-to-line positions of the bonding pads by 1/2 pitch. With this zigzag arrangement, more bonding pads become available in a semiconductor chip of the same size because the effective pitch of the bonding pads is reducible.
Japanese Patent Laid-Open Publication No. 29377/1993, for example, discloses a logic LSI with bonding pads employing such a zigzag arrangement.
The logic LSI as disclosed in the publication above is arranged such that, in the case of three layers of wiring, for example, two lines of bonding pads are arranged along the outer periphery of a semiconductor chip in a zigzag manner by shifting the line-to-line positions of the bonding pads by 1/2 pitch. The bonding pads are formed in a wide third layer of wiring and a narrow second layer of wiring, and outgoing wiring for connecting the bonding pads and internal circuits is formed in a first layer of wiring.
When two lines of bonding pads are arranged in a zigzag manner decreasing the pitch of the bonding pads causes the outgoing wiring of the bonding pads on the outer line side to overlap with the bonding pads on he inner line side, which results in forming a combined capacitance between the bonding pad and the outgoing wiring that have been overlapped.
In a case where the bonding pads are formed in the wide third layer of wiring and the narrow second layer of wiring as referred to in the patent laid-open publication cited above, two layers of layer-to-layer insulating films are held between the wide third layer of wiring for forming part of the bonding pad and the first layer of wiring for forming the outgoing wiring (the first layer-to-layer insulating film for electrically separating the first layer of wiring from the second layer of wiring and the second layer-to-layer insulating film for electrically separating the second layer of wiring from the third layer of wiring), whereby the combined capacitance between the bonding pad and outgoing wiring that have been overlapped is reduced. Moreover, the outgoing wiring and the bonding pad are not overlapped because the second layer of wiring forming part of the bonding pad is narrow. Consequently, no problem is posed about the combined capacitance between the second layer of wiring and the outgoing wiring.